For input/output (I/O) interfaces that exist between field programmable gate arrays (FPGAs) and dynamic random access memory (DRAM), I/O buffers driving signals from the FPGA to the DRAM (and vice versa) must be calibrated to compensate for any impedance discontinuity that may exist between the I/O buffer and board traces coupled between the FPGA and DRAM. Calibration of the I/O buffers is performed to reduce the noise being reflected back into the I/O buffer when during signal transmission.
Impedance discontinuity that exists between the I/O buffers and board traces may be due to process variation, temperature variation, and voltage variation. Currently, calibration of I/O buffers is done by connecting a precision resistor on-board (e.g., external to semiconductor die) and dedicating an I/O buffer of an I/O bank for performing calibration. The precision resistor is used to determine the amount of impedance discontinuity associated with the dedicated I/O buffer and the remaining I/O buffers of the I/O bank are calibrated accordingly. Using an on-board precision resistor increases implementation costs. Furthermore, dedicating an I/O buffer for calibration limits its ability to be used for another function.